VC04LC18V500DP [KYOCERA AVX]
Varistor, 18V, 0.02J, Surface Mount;
| 型号： | VC04LC18V500DP |
| 厂家： | 
KYOCERA AVX |
| 描述： | Varistor, 18V, 0.02J, Surface Mount 电阻器 |
| 文件： | 总2页 (文件大小：41K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
StaticGuard
AVX Multilayer Ceramic Transient Voltage Suppressors
ESD Protection for CMOS and Bi Polar Systems
GENERAL INFORMATION
• Typical ESD failure voltage for CMOS and/or Bi Polar is
• Low capacitance (<200pF) is required for high-speed
data transmission.
≥ 200V.
• 15kV ESD pulse (air discharge) per
IEC 1000-4-2, Level 4, generates < 20 millijoules of
energy.
• Low leakage current (IL) is necessary for battery
operated equipment.
PART NUMBER IDENTIFICATION (See page 2 for details)
Chips
Axials
V C 08 LC 18 A 500 R P
V A 10 LC 18 A 500 R L
TERMINATION FINISH:
X = Pt/Pd/Ag (Non-Plated)
P = Ni/Sn Alloy (Plated)
LEAD FINISH:
L = Copper Clad Steel,
Solder Coated
PACKAGING (Pcs/Reel)
CLAMPING VOLTAGE
ENERGY RATING
PACKAGING (Pcs/Reel)
CLAMPING VOLTAGE
ENERGY RATING
WORKING VOLTAGE (0-18V)
LOW CAPACITANCE DESIGN
CASE SIZE DESIGNATOR
CASE STYLE
WORKING VOLTAGE (0-18V)
LOW CAPACITANCE DESIGN
CASE SIZE DESIGNATOR
CASE STYLE
PRODUCT DESIGNATOR
PRODUCT DESIGNATOR
AVX
Part Number
Working
Voltage
Clamping
Voltage
Peak
Current
Transient
Energy
Capacitance
Inductance
Symbol
VWM
VC
Ipeak
Etrans
C
L
Volts
(max.)
Volts
(max.)
Amp
(max.)
Joules
(max.)
pF
(typ.)
nH
(typ.)
Units
0.5Vrms @:
1 MHz
di/dt =
100mA/ns
Test Condition
<10µA
8/20µS†
8/20µs
10/1000µS
VC04LC18V500 _ _
VC06LC18X500 _ _
VC08LC18A500 _ _
See specifications on page 3 and performance data on page 4.
≤18.0
≤18.0
≤18.0
≤18.0
50
50
50
50
20
30
30
30
.05
0.1
0.1
0.1
75
100
200
200
<1.0
<1.5
<1.7
<3.5
VC12LC18A500 _ _
*
L
VA10LC18A500 _
Termination Finish: X = Pt/Pd/Ag (Non-Plated)
P = Ni/Sn Alloy (Plated)
= Contact Factory for Availability
*
Lead Finish: L = Copper Clad Steel, Solder Coated
Packaging (Pcs/Reel): see page 2
VWM—Maximum steady-state DC operating voltage the varistor can maintain and not exceed 50µA leakage current
VC—Maximum peak voltage across the varistor measured at a specified pulse current and waveform
†Transient Energy Rating
<0.05 Joule
Pulse Current & Waveform
1A 8/20µS
0.1 Joule
2A 8/20µS
Ipeak—Maximum peak current which may be applied with the specified waveform without device failure
Etran—Maximum energy which may be dissipated with the specified waveform without device failure
C—Device capacitance measured with zero volt bias 0.5Vrms and 1MHz
L—Device inductance measured with a current edge rate of 100 mA/nS
Dimensions: Millimeters (Inches)
14
StaticGuard
AVX Multilayer Ceramic Transient Voltage Suppressors
ESD Protection for CMOS and Bi Polar Systems
TYPICAL PERFORMANCE DATA
StaticGuard ESD RESPONSE
IEC 1000-4-2 (8 Kv Contact Discharge)
VC06LC18X500 Capacitance Histogram
50
45
40
35
30
30%
25%
20%
VC08LC18A500
VC12LC18A500
VC06LC18X500
15%
10%
5%
0%
45
50
55
60
65
1
10
100
1000
10000
Capacitance (pF @ 1MHz & 0.5V)
Number of ESD Strikes
Measured Data
Calculated
VC08LC18A500 Capacitance Histogram
StaticGuard S21
DB
0
14%
14%
12%
VC12LC18A500
VC08LC18A500
12%
-10
-20
-30
-40
10%
8%
6%
4%
2%
0%
10%
8%
6%
4%
2%
0%
VC06LC18X500
61 63
65 67 69 71 73 75 77 79 81 83 85 87 89
Capacitance (pF)
0
500
1000
1500
2000
2500
Frequency (MHz)
1MHz, 0.5VRMS
Measured Data
Calculated Distribution
VI Curves - StaticGuard Products
VC12LC18A500 Capacitance Histogram
100
14%
14%
80
60
40
12%
12%
10%
8%
6%
4%
2%
0%
10%
8%
6%
4%
2%
0%
20
0
161 163 165 167 169 171 173 175 177 179 181 183 185 187 189
Capacitance (pF)
10-9
10-6
10-3
10+0
10+3
Current (A)
06LC
08LC
12LC
10LC
1MHz, 0.5VRMS
Measured Data
Calculated Distribution
15
相关型号：
VC04LC18V500WP
AVX Multilayer Ceramic Transient Voltage Suppressors ESD Protection for CMOS, Bi Polar and SiGe Based Systems
KYOCERA AVX
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